1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a high density and a large capacity.
2. Description of the Prior Art
Semiconductor memory devices which are currently employed include static memory devices basically consisting of flip-flops with about 6 transistors per one bit and dynamic memory devices using 1 to 3 insulated gate field effect transistors (IGFET) per one bit and requiring refreshment of the stored information. Another type of semiconductor memory device makes use of a variation of a threshold value caused by trapping an electric charge at a trap level in a gate insulator film on a channel of an IGFET, typically known as MAOS (Metal-Alumina-Silicon Oxide-Silicon) or MNOS (Metal-Silicon Nitride-Silicon Oxide-Silicon) having a 2-layer insulator film. In these memory devices, by applying a voltage between a gate electrode and a substrate or between a gate electrode and a channel, the conductivity between the source and the drain is varied or completely eliminated, or owing to a memory effect of the gate insulator film, it is possible to maintain the conductivity over a long period of time. Also in some memory devices, the floating gate is provided in a gate insulator film, and by injecting a charge into the floating gate by any appropriate means to induce a charge of opposite polarity to the injected charge on a surface of silicon, a conductivity between a source and the drain is varied. Upon injecting the charge into the floating gate, it can be injected from the side of a silicon substrate or from the side of an electrode by making use of a tunnel phenomenon or a Schottky effect, or else, an avalanche phenomenon is generated by providing an appropriate p-n junction on the substrate side to produce the so-called hot electrons and hot holes having a large energy, and thereby the charge can be injected as overcoming an energy barrier existing between the silicon substrate and a silicon oxide film.
If such type of nonvolatile memory transistors are arranged in a matrix form on a single semiconductor substrate, bit selection would become impossible upon reading, because a plurality of memory transistors on a bit line may become normally-on. Therefore, a normally-off transistor having a fixed gate threshold voltage must be connected in series to each memory transistor. However, such construction is disadvantageous for high density integration, because the number of memory transistors that can be assembled on one chip must be reduced one-half. Another factor for preventing high density integration is the requirement for electrical isolation between wirings or between elements, which presents a problem especially in the case of n-channel type elements which can operate at a high speed. Namely, each bit element must be substantially surrounded by the isolation region including a high-concentration impurity region having the same conductivity type as the substrate. For example, the high-impurity region having 2 .mu.m width is formed between a source region (bit line) of one element and a drain region (bit line) of an adjacent element, and the high-impurity region must be separated from the source or drain regions about 1 .mu.m, or more. Therefore, the elements must be separated from each other by 4 .mu.m or more. The above-described memory device employing MNOS's is disclosed, for example, in an article by Joe E. Brewer entitled "MNOS Density Parameters", IEEE Transactions on Electron Devices, Vol.Ed. 24, No. 5, May 1977, pp. 618 to 625 and in an article by Dov Frohman-Bentchkowsky entitled "The Metal-Nitride-Oxide-Silicon (MNOS) Transistor-Characteristics and Applications", Proceedings of the IEEE, Vol. 58, No. 8, August 1970, pp. 1207-1219.
In addition, the so-called mask-writing read-only memory device that is constructed by making use of insulated gate field effect transistors, has been heretofore widely used because it is simple in structure in that it is only necessary to array transistors in a two-dimensional manner to form a matrix. However, the read-only memory device in the prior art also had the same disadvantage as the aforementioned MNOS.
More recently, a new memory device has been proposed by G. F. Vanstone in a letter entitled "Metal-Nitride-Oxide-Silicon-Capacitor Arrays as Electrical and Optical Stores", Electronics Letters, Jan. 13, 1972, Vol. 8, No. 1, pp. 13-14. This memory device has a plurality of gates provided between the source and the drain. However, since this device is a MNOS type memory adapted to perform a CCD (Charged Coupled Device) operation, the resistance between the source and drain becomes inevitably high. Moreover, a high voltage must be applied to the gate electrodes for the CCD operation, and the stored information is badly affected by the high voltage.